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1 datasheet 25a/35a drmos module with diode emulation and ps4 isl99125b, isl99135b the isl99125b and isl99135b are high-performance drmos power modules designed for high-frequency power conversion. by combining a high-performance fet driver and mosfets in an advanced package, high-density dc/dc converters may be created. combined with an inte rsil pwm controller, a complete voltage regulator solution can be created with reduced external components and minimum overall pcb real estate. the isl99125b and isl99135b feature a three-state pwm input that, working together with intersil?s 5v pwm controllers (such as isl6398, isl9585x, isl637x, isl633x, isl636x, and isl68201), will provide a robust solution in the event of abnormal operat ing conditions. the isl99125b, isl99135b support high-efficiency operations not only at heavy loads, but al so at light loads via its diode emulation capability. diode emulation can be disabled for those applications where variab le frequency operation is not desired at light loads. isl99125b, isl99135b also featur e very low shutdown supply current (3a) to ensure the low power consumption, especially designed for imvp8 ps4 shutdown operation. related literature ? for a full list of related documents, visit our website - isl99125b and isl99135b product pages features ?v in range: 0v to 25v ? current capability: 25a (isl99125b), 35a (isl99135b) ? supports three-state 5.0v pwm input ?0.5 on-resistance and 4a sink current capability ? diode emulation for enhanc ed light-load efficiency ? ultra low shutdown supply current (3a) for ps4 operation ? low three-state hold-off time ? adaptive shoot-through protection ? integrated high-side gate-to-sour ce resistor to prevent self turn-on due to high input bus dv/dt ?v cc undervoltage lockout ? switching frequencies up to 2mhz ? pb-free (rohs compliant) ?3.5x5 qfn 24 ld package applications ? high-efficiency and high-density vrm and vrd ? core, graphic, and memory regulators for microprocessors ? high-density vr for server, networking, and cloud computing ? pol dc/dc converters and video gaming consoles figure 1. simplified application block diagram intersil pwm controller pwm phase boot +5v fccm shoot- through protection vcc vcc gnd gnd vin +12v gnd l out pwm fccm c out v out sw isl991x5 january 24, 2017 fn8848.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2016, 2017. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl99125b, isl99135b 2 fn8848.4 january 24, 2017 submit document feedback functional block diagram figure 2. functional block diagram gh boot shoot- through protection vcc vcc vin pwm logic por pwm zero detect sw gnd gl fccm sw gnd phase gl gh 20k ordering information part number ( notes 1 , 2 , 3 ) part marking temp range (c) current rating (a) pwm input (v) tape and reel (units) package (rohs compliant) pkg. dwg. # isl99125bdrz-t 125bdrz -40 to +85 25 5.0 3k 24 ld exposed pad 3.5x5 qfn l24.3.5x5w isl99135bdrz-t 135bdrz -40 to +85 35 5.0 3k 24 ld exposed pad 3.5x5 qfn l24.3.5x5w ISL68201-99125DEMO1Z 3.3v at 16a design with isl991 25b and the isl68201 digital hybrid pwm controller isl68201-99135demo1z 1.0v at 20a design with isl991 35b and the isl68201 digital hybrid pwm controller notes: 1. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), see product information pages for isl99125b , isl99135b . for more information on msl, see tech brief tb363 . table 1. key differences between family of parts part # current rating (a) pwm (v) thermal flag ocp flag imon tmon package p2p compatible used with 5.0v pwm power stage family isl99125b 25 5.0 no no no no 24 ld 3.5x5 qfn isl99135b analog controllers: isl633x, isl636x, isl637x, isl95829, isl9585x digital hybrid controllers: isl68201, isl6388/98 full digital controller: zl8802 phase doublers: isl6617, isl6617a isl99135b 35 5.0 no no no no 24 ld 3.5x5 qfn isl99125b isl99227b 60 5.0 yes yes yes yes 32 ld 5x5 pqfn isl99226b 3.3v pwm power stage family isl99140 40 3.3 yes no no no 40 ld 6x6 qfn ? n/a full digital controllers: isl68/69xxx, zl8802 digital hybrid controllers: isl68201, isl6388/98 (3.3v pwm setting) isl99227 60 3.3 yes yes yes yes 32 ld 5x5 pqfn isl99226a
isl99125b, isl99135b 3 fn8848.4 january 24, 2017 submit document feedback pin configuration isl99125b, isl99135b (24 ld qfn) top view 24 23 22 21 20 19 18 17 67 89101112 16 15 14 13 1 2 3 4 5 sw sw sw sw pwm fccm boot gh phase vin vin vin gnd gnd gnd gnd vcc vcc vin gnd gl gl gnd gnd vin pad2 gnd pad1 pin descriptions pin # pin name description 1 pwm pwm input of gate driver. the pwm signal can enter three distinct states during operation. connect this pin to the pwm output of the controller. 2 fccm input pin to enable or disable diode emulation. when fccm is low, diode emulation is allowed. when fccm is high, continuous conduc tion mode is forced. high impedance on the input (floating fccm) or keeping the pin at mid- level of vcc will shut down the device into ultra-low current mode (5v, 3 a). 3 boot floating bootstrap supply pin for the upper gate drive. place a high quality low esr ceramic capacitor (~0.1 f to 0.22 f/x7r) in close proximity across the boot and phase pins. 4 gh high-side gate drive output for monitoring/testing. no circuit connection needed. 5 phase return of bootstrap capacitor. internally connected to sw node. external connection is not needed. 6, 7, 8, 22, pad2 vin input of power stage. place a couple of high quality, low esr ceramic capacitors (10 f or higher, x5r or x7r) in close proxim ity across the vi n and gnd planes. 9, 10, 11, 12, 17, 18, 21, pad1 gnd power stage and logic bias supply return. connect directly to system ground plane. 13, 14, 15, 16 sw switching junction node between low- side and high-side mosfets. connect directly to output inductor. 19, 20 gl low-side gate drive output for monito ring/testing. no circuit connection needed. 23, 24 vcc +5v driver bias supply. place a hi gh quality, low esr ceramic capacitor (~1 f/ x5r~x7r) in close proximity from this pin to system ground plane.
isl99125b, isl99135b 4 fn8848.4 january 24, 2017 submit document feedback typical applications circuits with isl68201 figure 3. wide range input and output applications figure 4. 5v input application vsen rgnd csen csrtn gnd scl sda pgood en pgood en vcc pvcc vin lgin phase ntc i 2 c/ smbus/ pmbus 4.75 to 24v 0.5v to 5.5v iout prog1-4 salert vcc 7vldo vcc ntc 4.7f 1.0f 1.0f 0.1f 1.54k 10k ncp18xh103j03rb beta = 3380 4 boot pwm isl99135b ug lg pwm 100 fccm vcc v out < 7vldo 1.7v \ vcc 1.0f vsen rgnd csen csrtn gnd scl sda pgood en pgood en vcc pvcc vin lgin phase ntc i 2 c/ smbus/ pmbus 4.5 to 5.5v 0.5v to 2.5v iout prog1-4 salert vcc 7vldo vcc ntc 4.7f 1.0f 1.0f 0.1f 1.54k 10k ncp18xh103j03rb beta = 3380 4 pwm 100 fccm vcc v out < 7vldo 1.7v \ boot pwm isl99125b ug lg vcc 1.0f
isl99125b, isl99135b 5 fn8848.4 january 24, 2017 submit document feedback typical application circuit with isl95855 figure 5. typical application circuit with isl95855 ntc1 network is not needed if tms is used for vr1, gpu vr_enable vr_ready vcc sense_cpu vr_enable vr_ready sda sda alert# alert# sclk sclk gnd vcc vr_hot# vr_hot# +5v isl95855 pwm1_a cpu v core psys fccm_a pwm3_a comp_a vss sense_cpu vcc sense_sa vss sense_sa sa v core ntc_b fccm_b pwm_c fccm_c isump_c isumn_c comp_c fb_c rtn_c psys vin vin prog1 prog2 prog3 +5v prog4 isump_a isumn_a isen3_a isen2_a pwm2_a pwm1_b c prog5 imon_c isen1_a imon_a fb_a rtn_a vcc sense_gt gt v core vss sense_gt isump_b isumn_b isen1_b isen2_b pwm2_b v+5 comp_b fb_b rtn_b c c c v+5 imon_b ntc_a c vcc vin boot fccm isl99135 b pwm vcc vin boot fccm isl99135 b pwm vcc vin boot fccm isl99135 b pwm vcc vin boot fccm isl99135 b pwm vcc vin boot fccm isl99135 b pwm vcc vin boot fccm isl99135 b pwm vcc
isl99125b, isl99135b 6 fn8848.4 january 24, 2017 submit document feedback absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 30v supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v i/o voltage (v pwm , v fccm ) . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . . -0.3v to 33v (dc) or 36v (<20ns) boot to phase voltage (v boot-phase ) . . . . . . . . . . . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (gnd - 0.3v) to 30v gnd - 10v (<20ns pulse width, 10j) esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv charged device model (tested per jesd22-c101c) . . . . . . . . . . . . . 1kv latch-up (tested per jesd78c, class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) 24 ld qfn package ( notes 4 , 5 ) . . . . . . . . 10 3 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +125c supply voltage, v cc , pvcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% input supply voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 25v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high-effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = +25c; v in = 12v, v vcc = 5v unless otherwise noted. boldface limits apply across the recommended operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit v cc supply current standby bias supply current i vccsd pwm and fccm pin floating 3.3 4 a pwm pin floating, v fccm = 5v 80 a pwm pin floating, v fccm = 0v 120 a isl99125b bias supply current i vcc fccm = 5v, v pwm = 300khz, 10% duty cycle 12 ma isl99135b bias supply current fccm = 5v, v pwm = 300khz, 10% duty cycle 10 ma isl99125b bias supply current fccm = 5v, v pwm = 1mhz, 10% duty cycle 40 ma isl99135b bias supply current fccm = 5v, v pwm = 1mhz, 10% duty cycle 34 ma power-on reset and enable por rising threshold v porr 3.4 3.9 v por falling threshold v porf 2.3 2.9 v por hysteresis v porh 500 mv pwm input input current i pwm v pwm = 5v 250 a v pwm = 0v -250 a pwm rising threshold v pwmh v vcc = 5v 3.5 3.8 4.1 v pwm falling threshold v pwml v vcc = 5v 0.7 1.0 1.3 v tri-state shutdown window v cc = 5v 1.3 3.5 v fccm input input current i fccm v fccm = 5v 50 a v fccm = 0v 50 a fccm high rising threshold v vcc = 5v 2.8 3.6 v fccm low falling threshold v vcc = 5v 1.4 2.2 v
isl99125b, isl99135b 7 fn8848.4 january 24, 2017 submit document feedback tri-state shutdown window v vcc = 5v 2.2 2.8 v ps4 exit latency t ps4exit v vcc = 5v 15 s switching time gh turn-on propagation delay t pdhu v vcc = 5v, see figure 6 (gl low to gh high) 20 ns gh turn-off propagation delay t pdlu v vcc = 5v, see figure 6 (pwm low to gh low) 18 ns gl turn-on propagation delay t pdhl v vcc = 5v, see figure 6 (gh low to gl high) 20 ns gl turn-off propagation delay t pdll v vcc = 5v, see figure 6 (pwm high to gl low) 25 ns gh/gl exit tri-state propagation delay t pdts v vcc = 5v, see figure 6 (tri-state to gh/gl high) 35 ns pwm tri-state shutdown hold-off time t tsshd v cc = 5v 100 175 250 ns minimum gl on-time in dcm t lgmin v vcc = 5v 350 ns bootstrap diode forward voltage v vcc = 5v, forward bias current = 2ma 0.43 0.55 0.65 v notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization, and/or design. electrical specifications t a = +25c; v in = 12v, v vcc = 5v unless otherwise noted. boldface limits apply across the recommended operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit figure 6. timing diagram pwm gh gl t fl t pdhu t pdll t rl t tsshd t pdts t pdts t fu t ru t pdlu t pdhl t tsshd
isl99125b, isl99135b 8 fn8848.4 january 24, 2017 submit document feedback typical performance characteristics v cc = 5v, t a = +25c, unless otherwise noted figure 7. v out power stage efficiency (v in = 12v; 500khz; l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) figure 8. v out power stage dissipation (v in = 12v; 500khz; l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) figure 9. v out power stage efficiency (v in = 12v; v out =1.0v l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) figure 10. v out power stage dissipation (v in = 12v; v out =1.0v l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) figure 11. efficiency comparison of pwm mode and pfm enabled mode (v in = 12v, v out = 1.0v, l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) figure 12. efficiency comparison of pwm mode and pfm enabled mode (v in = 12v, v out = 2.5v, l out = 0.18h/0.17m ? /fp1008-180-r; include inductor and isl99135b losses) 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 30 35 load (a) 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v efficiency (%) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 load (a) 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v power dissipation (w) 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 0 5 10 15 20 25 30 35 load (a) 300khz 400khz 500khz 600khz 700khz 850khz 1mhz 1.5mhz efficiency (%) 0 2 4 6 8 10 0 5 10 15 20 25 30 35 load (a) 300khz 400khz 500khz 600khz 700khz 850khz 1mhz 1.5mhz power dissipation (w) -5 0 5 10 15 20 25 30 35 40 81 82 83 84 85 86 87 88 89 90 91 0 5 10 15 20 25 30 35 load (a) pwm mode pfm mode efficiency boost efficiency (%) efficiency boost (%) -10 0 10 20 30 40 50 85 86 87 88 89 90 91 92 93 94 95 0 5 10 15 20 25 30 35 load (a) pwm mode pfm mode efficiency boost efficiency (%) efficiency boost (%)
isl99125b, isl99135b 9 fn8848.4 january 24, 2017 submit document feedback figure 13. power stage efficiency (v in = 12v; 400khz l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses) figure 14. power stage dissipation (v in = 12v; 400khz l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses) figure 15. power stage efficiency (v in = 12v; v out = 3.3v l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses) figure 16. power stage dissipation (v in = 12v; v out = 3.3v l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses) figure 17. efficiency comparison of pwm mode and pfm enabled mode (v in = 12v, v out = 3.3v, l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses) figure 18. efficiency comparison of pwm mode and pfm enabled mode (v in = 12v, v out = 5.0v, l out = 0.47h/0.32m ? /we 744-301-047; include inductor and isl99125b losses)) typical performance characteristics v cc = 5v, t a = +25c, unless otherwise noted (continued) 76 78 80 82 84 86 88 90 92 94 96 98 0 5 10 15 20 25 load (a) 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v efficiency (%) 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 load (a) 0.8v 1.0v 1.2v 1.5v 1.8v 2.5v 3.3v 5.0v power dissipation (w) 86 87 88 89 90 91 92 93 94 95 96 0 5 10 15 20 25 load (a) 300khz 400khz 500khz 600khz 700khz 850khz 1mhz 1.5mhz efficiency (%) 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 load (a) 300khz 400khz 500khz 600khz 700khz 850khz 1mhz 1.5mhz power dissipation (w) -10 -5 0 5 10 15 20 25 30 35 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 load (a) pwm mode pfm mode efficiency boost efficiency (%) efficiency boost (%) -5 0 5 10 15 20 25 30 35 40 45 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 load (a) pwm mode pfm mode efficiency boost efficiency (%) efficiency boost (%)
isl99125b, isl99135b 10 fn8848.4 january 24, 2017 submit document feedback operation the isl99125b, isl99135b are optimized driver and power stage solutions for high-density synchronous dc/dc power conversion. the isl99125b and isl99135b include a high-performance driver, integrated schottky bootstrap diode, and mosfet pair optimized for high switching frequency buck voltage regulators. the isl99125b, isl99135b include a driver with advanced power management features that allow direct control of the lower mosfet an d diode emulation as well as imvp8 ps4 shutdown mode. power-on reset (por) during initial start-up, the v cc voltage rise is monitored. once the rising v cc voltage exceeds 3.5v (typic ally), normal operation of the driver is enabled. if v cc drops below the falling threshold of 2.95v (typically), operation of the driver is disabled. shoot-through protection prior to v cc exceeding its por level, the undervoltage protection function is activated and both gh and gl are held active low (off). once the v cc voltage surpasses the rising threshold (see ?electrical specifications? on page 6 ) the pwm and fccm signals are used to control both high-side and low-side mosfets. the rising edge on pwm initiates the turn-off of the lower mosfet. adaptive shoot-through circuitry monitors the gl voltage and determines a safe time for the upper mosfet to turn-on. this prevents the mosfets from conducting simultaneously. the falling pwm transition causes the upper fet to turn off and the lower fet to turn on. adaptive shoot-through circuitry monitors the gh to sw voltage to determine a safe time for the low-side mosfet turn-on. this prevents the mosfets from conducting simultaneously. should the driver have no bias voltage applied and be unable to actively hold the mosfets off, an integrated 20k resistor from the upper mosfet gate-to-source will aid in keeping the device in its off state. this can be especia lly critical in applications where the input voltage rises prior to the isl99125b and isl99135b v cc supply. tri-state pwm input the isl99125b and isl99135b supports a tri-level input on the pwm pin. should the pin be pulled into and remain in the tri-state window for a set hold-off time, the driver will force both mosfets to their off states. when the pwm signal moves outside the shutdown window, the driver immediately resumes driving the mosfets according to the pwm commands. this feature is utilized by intersil pwm controllers as a method of forcing both mosfets off. should the pwm input be left floating, the pin will be pulled into the tr i-state window internally and force both mosfets to a safe off state. the isl99125b and isl99135b?s tri-state levels are compatible with 5.0v pwm logic. fccm operation diode emulation allows for higher converter efficiency under light load situations. with diode emulation active (fccm pulled low), the isl99125b and isl99135b will detect the zero current crossing of the output inductor and turn off the low-side gate after the minimum lgate on-t ime of 350ns expires. this ensures that discontinuous conduc tion mode (dcm) is achieved to minimize losses. diode emulat ion is asynchronous to the pwm signal. therefore, the isl99125b and isl99135b will respond to the fccm input immediately after it changes state. this operation is compatible with the isl95825 vr12.5/12.6 controller for diode emulatio n operation and the isl68201 digital hybrid controller for pfm operation, significantly improving light-load efficiency. furthermore, compared to conventional drivers with fccm input, the isl99125b and isl99135b enters shutdown operation of both the high-side and low-side mosfet when the fccm pin enters its tri-state window. this mode reduces the total bias current to 3a and significantly reduces the power consumption at standby mode, which is required to support intel imvp8 ps4 shutdown operation and compatib le with isl95855, isl95857, isl95859, and isl95829 imvp8 controllers. for incompatible controllers without the fccm output pin such as isl6398, isl637x, isl633x, and isl636x, the isl99125b and isl99135b?s fccm pin sh ould be pulled to v cc . bootstrap function the isl99125b and isl99135b features an internal bootstrap schottky diode. a high quality ceramic capacitor should be placed in close proximity across boot and phase pins. the bootstrap capacitor can range between 0.1f~0.22f/x5r~x7r for normal buck switching applications. pcb layout considerations proper pcb layout will reduce noise coupling to other circuits, improve thermal performance and maximize the efficiency. the following is meant to lead to an optimized layout: ? place multiple 10f or greater ceramic capacitors directly at the device between vin and pgnd as indicated in figure 20 . this is the most critical decoupling and reduced parasitic inductance in the power switchin g loop. this will reduce overall electrical stress on the device as well as reduce coupling to pwm gh fccm t ps4exit 5v 5v 2.5v figure 19. ps4 exit timing diagram
isl99125b, isl99135b 11 fn8848.4 january 24, 2017 submit document feedback other circuits. best practice is to place the decoupling capacitors on the same pcb side as the device. ? connect gnd to the system ground plane with a large via array as close to the gnd pins as the design rules allow. this improves thermal and electrical performance. ? place vcc and boot-phase decoupling capacitors at the ic pins as shown in figure 20 . ? note that the sw plane connecting the isl99125b, isl99135b, and inductor must carry a full load current and will create resistive loss if not sized properly. however, it is also a very noisy node that should not be oversized or routed close to any sensitive signals. best practice is to place the inductor as close to the device as possible and thus, minimizing the required area for the sw connection. if one must choose a long route of either the v out side of the inductor or the sw side, choose the quiet v out side. best practice is to locate the isl99125b, isl99135b as close to the final load as possible and thus avoid noisy or lossy routes to the load. table 3. available evaluation boards evaluation boards description smbus/ pmbus/i 2 c ISL68201-99125DEMO1Z 3.3v at 16a design with isl99125b and the isl68201 digital hybrid pwm controller. yes isl68201-99135demo1z 1.0v at 20a design with isl99135b and the isl68201 digital hybrid pwm controller. yes figure 20. pcb layout for minimizing current loops 24 23 22 21 20 19 18 17 67 89101112 16 15 14 13 1 2 3 4 5 sw sw sw sw pwm fccm boot gh phase vin vin vin pgnd pgnd pgnd pgnd vcc nc vin gnd gl gl gnd gnd gnd pad1 vin pad2
isl99125b, isl99135b 12 fn8848.4 january 24, 2017 submit document feedback intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related docume ntation, and related parts, please see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure that you have the latest revision. date revision change january 24, 2017 fn8848.4 changed temperature range from: -10c to +85c to: -40c to +85c, in ordering information table on page 2 and in recommended operating conditions and electrical specifications table on page 6. january 12, 2017 fn8848.3 frst bullet in features on page 1 and in recommended operating conditions on page 6: changed "4.5v to 25v" to "0v to 25v". october 14, 2016 fn8848.2 updated figure 5 on page 5. october 3, 2016 fn8848.1 updated the related literature section on page 1. in ?absolute maximum ratings? on page 6, updated boot voltage from ?-0.3v to 33v? to ?-0.3v to 33v (dc) or 36v (20ns)?. august 26, 2016 fn8848.0 initial release
isl99125b, isl99135b 13 fn8848.4 january 24, 2017 submit document feedback package outline drawing l24.3.5x5w 24 lead power quad flat no-lead plastic package rev 0, 4/16 top view bottom view c 0.25 pin #1 dot by marking e l l2 b f d a1 a2 l1 l3 e l4 l5 a 0.50 0.000 0.175 0.375 1.699 1.924 2.600 1.855 2.050 2.600 0.000 0.375 2.125 0.375 1.069 2.175 1.85 1.30 1.11 1.125 1.125 1.85 1.850 1.325 0.725 0.331 1.225 0.25 0.450 0.675 0.95 0.88 1.10 0.078 0.177 1.550 1.388 0 . 3 5 side view side view recommended land pattern unit: mm symbols millimeter min typ max a 1.00 1.10 1.20 a1 0.00 - 0.05 a2 0.20 ref. e 4.90 5.00 5.10 e1 1.63 1.73 1.83 e2 1.15 1.25 1.35 d1 1.65 1.75 1.85 d 3.40 3.50 3.60 l 0.35 0.40 0.45 l1 0.22 0.27 0.32 l2 0.30 0.35 0.40 l3 0.58 0.63 0.68 l4 1.02 1.12 1.22 l5 0.58 0.63 0.68 b 0.20 0.25 0.30 d 0.33 0.38 0.43 f 0.70 0.75 0.80 e0.50 bsc notes: 1. controlling dimension is millimeter. 2. converted inch dimensions are not necessarily exact. d d1 e1 e2 0 . 6 0 1.47 for the most recent package outline drawing, see l24.3.5x5w .

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